MOSIS Chip Design and Manufacture

I was given the wonderful opportunity to not only develop a skillset using Cadence, a VLSI CAD Suite, but was also able to layout a large variety of structures to get manufactured in On Semiconductor's C5 process. These structures ranged from basic MOSFETs to a full 8-bit loadable resettable up/down counter. After receiving the chips back from MOSIS, as part of my research position, I was tasked with characterizing each of the respective groups chips so that quality reports may be sent back to the manufacturer. Not only did this give me added experience, but it gave me the unique opportunity to verify the designs and layout of my groups chip. All structures on the chip functioned correctly and as designed. 

All of the labs for the class have been listed in the links below, as well as, the link to the respective lab in which these chips were developed on Cadence. It is here where one will be able to compare before/after manufacturing. 

Digital Electronics Lab Reports

Test Chip Layout for Submission to MOSIS for Fabrication

Fig. 1 - Overall Structure Layout in the Chip Padframe

Fig. 2 - Cadence VLSI Cad Chip Layout

Fig 3. - Actual Manufactured Chip underneath a microscope

Fig 4. - Ring Oscillator Structure

Fig. 5 - Logic Gate Structures

Fig. 6 - 8-Bit Loadable/Resettable Counter Internals

Fig. 7 - Counter Close-up

Fig. 8 - Logic and Ring Oscillator Close-Up